1. Field of the Invention
The present invention relates to an one-time programmable cell, a semiconductor integrated circuit including the same, and data judging method thereof.
2. Description of Related Art
An OTP (One-time programmable) cell is widely applied as a single memory or a memory array in a semiconductor integrated circuit. For instance, information written in the OTP cell array is used as a chip ID, a setting parameter, or the like.
A configuration of an OTP cell is disclosed in Japanese Unexamined Patent Application Publication No. 2008-204600, as a prior art. FIG. 6 shows the configuration of an OTP cell 1 of Japanese Unexamined Patent Application Publication No. 2008-204600. As shown in FIG. 6, the OTP cell 1 includes an anti-fuse element ANTFS1, PMOS transistors MP1 and MP2, and a detection circuit 10.
The PMOS transistor MP1 is connected between nodes N1 and N3. A reading control signal RD_CNTL is supplied to a gate of the PMOS transistor MP1. The PMOS transistor MP2 is connected between nodes N2 and N3. A writing control signal WR_CNTL is supplied to a gate of the PMOS transistor MP2. The anti-fuse element ANTFS1 is connected between the node N3 and a ground terminal GND.
The detection circuit 10 includes an inverter circuit IV11. An input terminal of the inverter circuit IV11 is connected to the node N3. An output voltage VOUT is output from an output terminal of the inverter circuit IV11. A power supply voltage VDD is supplied to the node N1, and a high voltage VPP (VPP>VDD) is supplied to the node N2.
The OTP cell 1 performs a fuse programming operation by destroying an insulation film of the anti-fuse element ANTFS1. The fuse programming operation of the OTP cell 1 is briefly explained below.
First, when data is written into the anti-fuse element ANTFS1, the writing control signal WR_CNTL is set to a low level and the reading control signal RD_CNTL is set to a high level. Thus, the PMOS transistor MP2 enters an on state and the PMOS transistor MP1 enters an off state. Then, the nodes N2 and N3 are connected electrically, and the node N1 and N3 are electrically disconnected. Therefore, the high voltage VPP is applied to both ends of the anti-fuse element ANTFS1.
The High voltage VPP is a voltage that exceeds a breakdown voltage of an oxide film of the anti-fuse element ANTFS1. For this reason, the oxide film of the anti-fuse element ANTFS1 is destroyed, and the node N3 and the ground terminal GND are in a conduction state. When the insulation film (oxide film) of the anti-fuse element ANTFS1 is destroyed and the data writing is carried out, the anti-fuse element ANTFS1 has resistance value in a range of several kΩ to hundreds of kΩ depending on the destruction state of the insulation film.
Next, when the data written in the anti-fuse element ANTFS1 is read, the writing control signal WR_CNTL is set to the high level and the reading control signal RD_CNTL is set to the low level. Thus, the PMOS transistor MP2 enters the off state and the PMOS transistor MP1 enters the on state. Then, the nodes N2 and N3 are electrically disconnected, and the nodes N1 and N3 are connected electrically. Therefore, the power supply voltage VDD is applied to both ends of the anti-fuse element ANTFS1. As a result, a current flows to the ground terminal GND through the node N1, the PMOS transistor MP1, the node N3, and the anti-fuse element ANTFS1, the insulation film of which is destroyed.
The inverter circuit IV11 buffers a voltage VN3 of the node N3 according to the current that flows through the node N1 to the ground terminal, and outputs the voltage as the voltage VOUT.
Therefore, when the data is not written in the anti-fuse element ANTFS1, the voltage VN3 of the node N3 becomes substantially equal to the power supply voltage VDD and the output voltage VOUT becomes low level. Contrarily, when the data is written in the anti-fuse element ANTFS1, the voltage VN3 of the node N3 decreases to the ground voltage GND side and the output voltage VOUT becomes high level depending on the destruction state of the insulation film of the anti-fuse element ANTFS1.